基于FPGA的数字下变频设计+文献综述
论文首先研究了信号正交分解理论、信号采样理论、多速率信号处理理论等数字下变频的理论基础，并在此基础上对数字下变频的结构、工作原理及影响数字下变频性能的主要因素进行了分析。然后进一步深入研究了数字下变频关键模块NCO与FIR滤波器的工作原理和实现算法。最后，调用QuartusII IP核及运用verilog HDL语言对数字下变频系统的各模块进行编程实现，并在系统硬件平台Altera EP3SE110上以90MHz采样频率，对中频频率为70MHz的信号实现了下变频处理，成功设计了基于FPGA的数字下变频。5746
关键词 数字下变频 NCO FIR滤波器 FPGA
毕业设计说明书（论文）外文摘要
Title Design of Digital Down Converter based on FPGA
Abstract
With the rapid development of microelectronic technology, computer technology and communication technology, digital down converter(DDC) has been widely used as a bridge which links the front-end ADC device and the back-end universal DSP device in the system of software defined radio. And the design of DDC based on FPGA has higher flexibility and lower costs, and thus, has become the main method of DDC implementation.
Firstly, this thesis studied the base theory related to DDC such as signal orthogonal decomposition theory, sampling theory and multi-rate signal processing. Then we introduced the structure and the working principle of DDC. Based on this, we analyzed the main factors which impact the DDC performance and the working principle and implementation algorithm of NCO and FIR filter that are the key modules in DDC. Finally, we used the QuartusII IP core and the Verilog HDL language to design and program modules of DDC and did down-conversion processing to a signal whose intermediate frequency is 70MHz with a sampling frequency of 90MHz on the hardware platform based on Altera EP3SE110.Successfully we designed the DDC based on FPGA.
Keywords DDC NCO FIR filter FPGA
目 次
1 绪论 1
1.1 课题背景 1
1.2 数字下变频的发展现状 2
1.3 本文的主要工作 3
2 数字下变频理论基础与结构分析 4
2.1 信号正交分解理论 4
2.2 信号采样理论 9
2.3 多速率信号处理理论 12
2.4 数字下变频的结构与性能 18
2.5 本章小结 19
3 数字下变频关键模块实现算法的研究 19
3.1 NCO模块实现算法分析 19
3.2 FIR模块实现算法分析 23
3.3 本章小结 25
4 数字下变频系统的设计与实现 26
4.1 数字下变频系统硬件平台 26
4.2 数字下变频系统FPGA实现 29
4.3 系统测试结果 35
4.4 本章小结 37
结 论 38
致 谢 39
参考文献 40
1 绪论
1.1 课题背景
近年来，随着微电子技术的迅猛发展，数字逻辑器件如FPGA和通用DSP芯片的逻辑规模越来越大，处理速度越来越快，性能迅速提高。基于软硬件编程方式来实现无线功能的软件无线电技术日渐成熟，被越来越广泛的应用于蜂窝通信及各种军用和民用的无线系统中[ ]。