基于SOC技术的等精度频率计设计+源码+流程图(11)
图5-5 程序流程图
VHDL程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XZ IS
PORT (CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUTCLK: OUT STD_LOGIC);
END XZ;
ARCHITECTURE RT OF XZ IS
SIGNAL COUNT:INTEGER:=0;
SIGNAL N:INTEGER;
BEGIN
PROCESS(CLK,A)
BEGIN
CASE A IS
WHEN"0000"=>N<=4;
WHEN"0001"=>N<=8;
WHEN"0010"=>N<=16;
WHEN"0011"=>N<=32;
WHEN"0100"=>N<=64;
WHEN"0101"=>N<=128;
WHEN"0110"=>N<=256;
WHEN"0111"=>N<=512;
WHEN"1000"=>N<=1024;
WHEN"1001"=>N<=2048;
WHEN"1010"=>N<=4096;
WHEN"1011"=>N<=8192;
WHEN"1100"=>N<=16384;
WHEN"1101"=>N<=32768;
WHEN"1110"=>N<=262144;
WHEN"1111"=>N<=200000000;
END CASE;
IF (CLK'EVENT AND CLK='1') THEN
IF (COUNT=N-1) THEN
COUNT<=0;
ELSE
COUNT<=COUNT+1;
IF COUNT<(N/2) THEN
OUTCLK<='0';
ELSE
OUTCLK<='1';
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
编译生成的模块文件如图5-6所示。
图5-6 分频器的模块文件